HDL Design Entry EASE 7.4.R6 (Windows/Linux) | 36.78/43.2 MB
EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you're creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language - VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project.
Features & Benefits
- Graphical design environment with automated generation of hierarchical VHDL or Verilog code
- Push-button import of legacy Verilog or VHDL designs and extraction of graphical hierarchy
- Adheres to state of the art Windows look and feel for intuitive operation
- Standards compliant (IEEE-1076-87&93 VHDL and IEEE-1364 Verilog)
- True multi-user design environment and associated version control, managed by a sophisticated design environment browser
- Integrates smoothly with the industry's most popular simulators and synthesis tools
- Platform independent database
- Integrated HDL language editor
- Hot error reporting
Project Browser
The Project Browser provides a good overview and offers easy access to the design elements. The browser offers three views: the Database View shows a tree of all elements in your project, the File View shows all HDL files in the project and their status and the Hierarchical View shows the HDL hierarchy of your project. It also provides many status details of the different objects, like verification status, 'instantiated from' info, version number and more. From the browser, all objects can be opened in their respective editor (block, state, truth table or text editor).
The Hierarchical View shows the hierarchy on the selected entity, module or configuration. It allows you to create or delete configurations. Here you can also changes the binding of an architecture to a component when having multiple architectures for an entity.
Block Diagram Editor
The block diagram editor allows you to easily decompose your system into functional blocks. It is up to you how detailed you want to make the decomposition. Each block can be implemented using one of the four available editors. Facilitating an abstraction level between block diagrams and plain HDL code, the block diagram editor allows you to graphically represent VHDL processes or Verilog always statements. They can be implemented using state diagrams, truth tables or HDL text. This approach visualizes the data flow inside a single diagram.
State Diagram Editor
The state diagram editor supports Moore, Mealy and mixed state machines. Any valid VHDL expression or Verilog statement can be used to define actions and transition conditions. Transitions can be synchronous or asynchronous; outputs can be clocked or combinatorial. The state diagram editor supports a variety of state assignment methods, including binary, gray, one-hot and two-hot. User defined assignment is also supported. The generated HDL is optimized for time and area to achieve the best possible synthesized design from leading synthesis tools.
